Search Result for "nibble mode dram":

The Free On-line Dictionary of Computing (30 December 2018):

Nibble Mode DRAM A standard DRAM where four successive bits can be clocked out of the single data line by successive pulses on the CAS\ line while RAS\ is active. A column address is only required for the first bit. This mode is now unfashionable but can be found on some older 64 kilobit and 256 kilobit chips. (1997-12-03)